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? 1999 scenix semiconductor, inc. all rights reserved. - 1 - www.scenix.com scenix? and the scenix logo are trademarks of scenix semiconductor, inc. i 2 c? is a trademark of philips corporation pic? is a registered trademark of microchip technology, inc. microchip? is a registered trademark of microchip technology, inc. sx-key? is a trademark of parallax, inc. microwire? is a trademark of national semiconductor corporation all other trademarks mentioned in this document are property of their respec- tive companies. preliminary may 30, 1999 devices with datcode axyywwxx sx18ac / sx20ac / sx28ac high-performance 8-bit microcontrollers with ee/flash program memory and in- sy stem programming capability 1.0 product overview 1.1introduction the sx18ac, sx20ac, and sx28ac are members of the sx family of high-performance 8-bit microcontrollers fabricated in an advanced cmos process technology. the advanced process, combined with a risc-based architecture, allows high-speed computation, flexible i/o control, and efficient data manipulation. throughput is enhanced by operating the device at frequencies up to 50 mhz and by optimizing the instruction set to include mostly single-cycle instructions. on-chip functions include a general-purpose 8-bit timer with prescaler, an analog comparator, a brown-out detec- tor, a watchdog timer, a power-save mode with multi- source wakeup capability, an internal r/c oscillator, user-selectable clock modes, and high-current outputs. 1.2key features ? 50 mips performance at 50 mhz oscillator frequency ? 2048 x 12 bits ee/flash program memory rated for 10,000 rewrite cycles ? 136 x 8 bits sram ? in-system programming capability through osc pins ? internal rc oscillator with configurable rate from 31.25 khz to 4 mhz, + 8 % accuracy ? user selectable clock modes: ? internal rc oscillator ? external oscillator ? crystal/resonator options ? external rc oscillator (continued on page 3) figure1-1. block diagram interrupt miwu port b comp power-on reset reset 8-bit watchdog timer (wdt) 8-bit timer rtcc 8 8 8 port c 8 8 port a 8 4 internal data bus in-system debugging in-system programming 2k x 12 eeprom system clock brown-out miwu mclr osc driver 4mhz internal rc osc clock select ? 4 or ? 1 136 bytes sram address write data read data instruction w fsr status pc mode option system clock osc1 osc2 fetch 8 8 12 address 12 8 8 8 8 alu 8 8 8 3 rtcc analog 8 or interrupt stack pc 3 level decode executive write back iread stack prescaler for rtcc prescaler for wdt instruction pipeline
? 1999 scenix semiconductor, inc. all rights reserved. - 2 - www.scenix.com sx18ac / sx20ac / sx28ac table of contents 1.0 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2.1 cpu features . . . . . . . . . . . . . . . . . . . . . 3 1.2.2 i/o features . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 programming and debugging support . . . . . . . . . . 3 1.5 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.0 connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.0 port descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 reading and writing the ports . . . . . . . . . . . . . . . . . 6 3.1.1 read-modify-write considerations . . . . . 7 3.2 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2.1 mode register . . . . . . . . . . . . . . . . . . . . 8 3.2.2 port configuration registers . . . . . . . . . . 8 3.2.3 port configuration upon reset . . . . . . . . 9 4.0 special-function registers . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 pc register (02h) . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 status register (03h) . . . . . . . . . . . . . . . . . . . . . 10 4.3 optionregister . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.0 device configuration registers . . . . . . . . . . . . . . . . . . . . . 12 5.1 fuse word (read/program at fffh in main memory map) 12 5.2 fusex word (read/program via programming command) 13 5.3 device word (hard-wired read-only) . . . . . . . . 13 6.0 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1.1 program counter . . . . . . . . . . . . . . . . . . 14 6.1.2 subroutine stack . . . . . . . . . . . . . . . . . . 14 6.2 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2.1 file select register (04h) . . . . . . . . . . . 14 7.0 power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 multi-input wakeup . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 port b miwu/interrupt configuration . . . . . . . . . . . 17 8.0 interrupt support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9.0 oscillator circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 xt, lp or hs modes . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 external rc mode . . . . . . . . . . . . . . . . . . . . . . . . . 21 9.3 internal rc mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.0 real time clock (rtcc)/watchdog timer . . . . . . . . . . . . . 21 10.1 rtcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.2 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 the prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11.0 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 12.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 13.0 brown-out detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 14.0 register states upon different reset operations . . . . . . . 26 15.0 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15.1 instruction set features . . . . . . . . . . . . . . . . . . . . . 27 15.2 instruction execution . . . . . . . . . . . . . . . . . . . . . . . 27 15.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 27 15.4 ram addressing . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.5 the bank instruction . . . . . . . . . . . . . . . . . . . . . . . 28 15.6 bit manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 15.7 input/output operation . . . . . . . . . . . . . . . . . . . . . . 28 15.8 increment/decrement . . . . . . . . . . . . . . . . . . . . . . . 28 15.9 loop counting and data pointing testing . . . . . . . 28 15.10 branch and loop call instructions . . . . . . . . . . . . . 28 15.10.1 jump operation . . . . . . . . . . . . . . . . . . . 28 15.10.2 page jump operation . . . . . . . . . . . . . . 29 15.10.3 call operation . . . . . . . . . . . . . . . . . . . . 29 15.10.4 page call operation . . . . . . . . . . . . . . . . 29 15.11 return instructions . . . . . . . . . . . . . . . . . . . . . . . . . 29 15.12 subroutine operation . . . . . . . . . . . . . . . . . . . . . . . 29 15.12.1 push operation . . . . . . . . . . . . . . . . . . . 29 15.12.2 pop operation . . . . . . . . . . . . . . . . . . . . 30 15.13 comparison and conditional branch instructions . 30 15.14 logical instruction . . . . . . . . . . . . . . . . . . . . . . . . . 30 15.15 shift and rotate instructions . . . . . . . . . . . . . . . . . 30 15.16 complement and swap . . . . . . . . . . . . . . . . . . . . 30 15.17 key to abbreviations and symbols . . . . . . . . . . . . . 30 16.0 instruction set summary table . . . . . . . . . . . . . . . . . . . . . . 31 16.1 equivalent assembler mnemonics . . . . . . . . . . . . . 34 17.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . 35 17.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36 17.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.4 comparator dc and ac specifications . . . . . . . . . 38 18.0 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
? 1999 scenix semiconductor, inc. all rights reserved. - 3 - www.scenix.com sx18ac / sx20ac / sx28ac 1.2 key features (continued) ? analog comparator ? brown-out detector (on/off, programmable trip level) ? multi-input wakeup (miwu) on eight pins ? fast lookup capability through run-time readable code ? complete development tool support available through parallax 1.2.1 cpu features ? fully static design ? dc to 50 mhz operation ? 20 ns instruction cycle time ? mostly single-cycle instructions ? selectable 8-level deep hardware subroutine stack ? single-level interrupt stack ? fixed interrupt response time: 60 ns int., 100 ns ext. at 50 mhz (turbo mode) ? hardware context save/restore for interrupt ? designed to be pin-compatible and upward code-com- pitable with the pic16c5x ? 1.2.2 i/o features ? software-selectable i/o configuration ? each pin programmable as an input or output ? ttl or cmos level selection on inputs ? internal weak pull-up selection on inputs ? schmitt trigger inputs on port b and port c ? all outputs capable of sinking/sourcing 30 ma ? symmetrical drive on port a outputs (same v drop +/-) 1.3architecture the sx devices use a modified harvard architecture. this architecture uses two separate memories with sepa- rate address buses, one for the program and one for data, while allowing transfer of data from program mem- ory to sram. this ability allows accessing data tables from program memory. the advantage of this architec- ture is that instruction fetch and memory transfers can be overlapped with a multi-stage pipeline, which means the next instruction can be fetched from program memory while the current instruction is being executed using data from the data memory. the sx family implements a four-stage pipeline (fetch, decode, execute, and write back), which results in execu- tion of one instruction per clock cycle. at the maximum operating frequency of 50 mhz, instructions are executed at the rate of one per 20-ns clock cycle. 1.4programming and debugging support the sx devices are currently supported by for third party tool vendors . th e tool s provide an integrated develop- ment environment including editor, macro assembler, debugger, and programmer. 1.5applications emerging applications and advances in existing ones require higher performance while maintaining low cost and fast time-to-market. the sx devices provide solutions for many familiar appli- cations such as process controllers, electronic appli- ances/tools, security/monitoring systems, and personal communication devices. in addition, the enhanced throughput allows efficient development of software mod- ules called virtual peripheral tm modules to replace on- chip hardware peripherals. the concept of virtual periph- eral tm provides benefits such as using a more simple device, reduced component count, fast time to market, increased flexibility in design, and ultimately overall sys- tem cost reduction. some examples of virtual peripheral tm modules are: ? serial/ parallel interfaces such as i 2 c?, microwire?, spi, dmx-512, x-10, and ir transceivers ? frequency generation and measurement ? spectrum analysis ? multi-tasking, interrupts, and networking ? resonance loops ? dram drivers ? music and voice synthesis ? ppm/pwm output ? delta/sigma adc ? dtmf i/o and call progress ? 300/1200 baud modem ? quadrature encoder/decoder ? proportional integral derivative (pid) and servo control ? video controller
? 1999 scenix semiconductor, inc. all rights reserved. - 4 - www.scenix.com sx18ac / sx20ac / sx28ac 2.0connection diagrams 2.1pin assignments 2.2pin descriptions ssop 1 2 3 4 5 6 7 8 16 15 rc4 rc3 rb6 rb5 sx 28-pin osc2 rc7 rc6 rc5 v dd v dd ra2 ra3 rb0 rb1 rb2 rb3 rb4 vss mclr osc1 rc2 rc1 rc0 rb7 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 vss rtcc ra0 ra1 1 2 3 4 5 6 7 8 16 15 rc4 rc3 rb6 rb5 sx 28-pin osc2 rc7 rc6 rc5 n.c. vss ra2 ra3 rb0 rb1 rb2 rb3 rb4 mclr osc1 rc2 rc1 rc0 rb7 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 rtcc v dd ra0 ra1 n.c. dip/soic 1 2 3 4 5 6 7 8 16 15 rb5 rb4 sx 20-pin osc2 rtcc ra 0 rb0 rb1 rb2 rb3 mclr osc1 v dd v dd rb7 rb6 9 10 14 13 12 11 20 19 18 17 ra2 ra3 vss ra1 vss ssop 1 2 3 4 5 6 7 8 16 15 rb5 rb4 sx 18-pin osc2 rtcc ra 0 rb0 rb1 rb2 rb3 mclr osc1 v dd rb7 rb6 9 10 14 13 12 11 18 17 ra2 ra3 ra1 vss dip/soic name pin type input levels description ra0 i/o ttl/cmos bidirectional i/o pin; symmetrical source / sink capability ra1 i/o ttl/cmos bidirectional i/o pin; symmetrical source / sink capability ra2 i/o ttl/cmos bidirectional i/o pin; symmetrical source / sink capability ra3 i/o ttl/cmos bidirectional i/o pin; symmetrical source / sink capability rb0 i/o ttl/cmos/st bidirectional i/o pin; comparator output; miwu input rb1 i/o ttl/cmos/st bidirectional i/o pin; comparator negative input; miwu input rb2 i/o ttl/cmos/st bidirectional i/o pin; comparator positive input; miwu input rb3 i/o ttl/cmos/st bidirectional i/o pin; miwu input rb4 i/o ttl/cmos/st bidirectional i/o pin; miwu input rb5 i/o ttl/cmos/st bidirectional i/o pin; miwu input rb6 i/o ttl/cmos/st bidirectional i/o pin; miwu input rb7 i/o ttl/cmos/st bidirectional i/o pin; miwu input rc0 i/o ttl/cmos/st bidirectional i/o pin rc1 i/o ttl/cmos/st bidirectional i/o pin rc2 i/o ttl/cmos/st bidirectional i/o pin rc3 i/o ttl/cmos/st bidirectional i/o pin rc4 i/o ttl/cmos/st bidirectional i/o pin rc5 i/o ttl/cmos/st bidirectional i/o pin rc6 i/o ttl/cmos/st bidirectional i/o pin rc7 i/o ttl/cmos/st bidirectional i/o pin rtcc i st input to real-time clock/counter mclr i st master clear reset input ? active low osc1/in/vpp i st crystal oscillator input ? external clock source input osc2/out o cmos crystal oscillator output ? in r/c mode, internally pulled to v dd through weak pull-up v dd p ? positive supply pin vss p ? ground pin note: i = input, o = output, i/o = input/output, p = power, ttl = ttl input, cmos = cmos input, st = schmitt trigger input, miwu = multi-input wakeup input
? 1999 scenix semiconductor, inc. all rights reserved. - 5 - www.scenix.com sx18ac / sx20ac / sx28ac 2.3part numbering table2-1. ordering information device pins i/o ee/flash (words) ram (bytes) sx18ac/so 18 12 2k 136 sx18ac/dp 18 12 2k 136 sx20ac/ss 20 12 2k 136 sx28ac/so 28 20 2k 136 sx28ac/dp 28 20 2k 136 sx28ac/ss 28 20 2k 136 figure2-1. part number reference guide sx18acxx-li/so package type extended temperature low voltage memory size feature set pin count scenix a = 512 word b = 1k word c = 2k word d = 4k word speed blank = 50 mhz 75 = 75 mhz 100 = 100 mhz dp = dip so = sop ss = ssop tq = thin pqfp pq = pqfp blank = 2.5v - 5.5v l = low voltage (tbd) blank = 0 c to + 70 c i = -40 c to +85 c
? 1999 scenix semiconductor, inc. all rights reserved. - 6 - www.scenix.com sx18ac / sx20ac / sx28ac 3.0port descriptions the device contains a 4-bit i/o port (port a) and two 8-bit i/o ports (port b, port c). port a provides symmetrical drive capability. each port has three associated 8-bit reg- isters (direction, data, ttl/cmos select, and pull-up enable) to configure each port pin as hi-z input or output, to select ttl or cmos voltage levels, and to enable/dis- able the weak pull-up resistor. the upper four bits of the registers associated with port a are not used. the least significant bit of the registers corresponds to the least significant port pin. to access these registers, an appro- priate value must be written into the mode register. upon power-up, all bits in these registers are initialized to ?1?. the associated registers allow for each port bit to be indi- vidually configured under software control as shown below: 3.1reading and writing the ports the three ports are memory-mapped into the data mem- ory address space. to the cpu, the three ports are avail- able as the ra, rb, and rc file registers at data memory addresses 05h, 06h, and 07h, respectively. writing to a port data register sets the voltage levels of the corre- sponding port pins that have been configured to operate as outputs. reading from a register reads the voltage lev- els of the corresponding port pins that have been config- ured as inputs. table3-1. port configuration data direction registers: r a, rb, rc ttl/cmos select registers: lvl_a, lvl_b , l vl_ c pullup enable registers: plp_a, plp_b , p lp_ c 0 1 0 1 0 1 output hi-z input cmos ttl enable disable figure3-1. port a configuration mode ra ra data lvl_a 0 = output 1 = hi-z input wr wr 0 = cmos 1 = ttl rd ttl buffer cmos buffer v dd pullup port a pin i n t e r n a l d a t a b u s m u x m o d e = 0 f m o d e = 0 e m o d e = 0 d wr direction plp_a 0 = pullup enable 1 = pullup disable port a input wr
? 1999 scenix semiconductor, inc. all rights reserved. - 7 - www.scenix.com sx18ac / sx20ac / sx28ac for example, suppose all four port a pins are configured as outputs and with ra0 and ra1 to be high, and ra2 and ra3 to be low: the second ?mov? instruction in this example writes the port a data register (ra), which controls the output levels of the four port a pins, ra0 through ra3. because port a has only four i/o pins, only the four least significant bits of this register are used. the four high-order register bits are ?don?t care? bits. port b and port c are both eight bits wide, so the full widths of the rb and rc registers are used. when a write is performed to a bit position for a port that has been configured as an input, a write to the port data register is still performed, but it has no immediate effect on the pin. if later that pin is configured to operate as an output, it will reflect the value that has been written to the data register. when a read is performed from a bit position for a port, the operation is actually reading the voltage level on the pin itself, not necessarily the bit value stored in the port data register. this is true whether the pin is configured to operate as an input or an output. therefore, with the pin configured to operate as an input, the data register con- tents have no effect on the value that you read. with the pin configured to operate as an output, what is read gen- erally matches what has been written to the register. 3.1.1 read-modify-write considerations caution must be exercised when performing two succes- sive read-modify-write instructions (setb or clrb oper- ations) on i/o port pin. input data used for an instruction must be valid during the time the instruction is executed, and the output result from an instruction is valid only after that instruction completes its operation. unexpected results from successive read-modify-write operations on i/o pins can occur when the device is running at high figure3-2. port b, port c configuration mode rb or rc plp_b or plp_c lvl_b or lvl_c 0 = output 1 = hi-z input wr 0 = pullup enable 1 = pullup disable wr 0 = cmos 1 = ttl rd port b: input, miwu, comparator v dd pullup resistor ( ~ 20k w ) port b or i n t e r n a l d a t a b u s m u x m o d e = 0 f m o d e = 0 e m o d e = 0 d m o d e = 0 c wr st_b or st_c wr 0 = schmitt trigger enable 1 = schmitt trigger disable port c: input only ttl buffer cmos buffer m u x port c pin schmitt trigger buffer direction rb or rc wr data ~ ~ mov w,#$03 ;load w with the value 03h ;(bits 0 and 1 high) mov $05,w ;write 03h to port a data ;register
? 1999 scenix semiconductor, inc. all rights reserved. - 8 - www.scenix.com sx18ac / sx20ac / sx28ac speeds. although the device has an internal write-back section to prevent such conditions, it is still recom- mended that the user program include a nop instruction as a buffer between successive read-modify-write instructions performed on i/o pins of the same port. also note that reading an i/o port is actually reading the pins, not the output data latches. that is, if the pin output driver is enabled and driven high while the pin is held low externally, the port pin will read low. 3.2port configuration each port pin offers the following configuration options: ? data direction ? input voltage levels (ttl or cmos) ? pullup type (pullup resistor enable or disable) ? schmitt trigger input (for port b and port c only) port b offers the additional option to use the port pins for the multi-input wakeup/interrupt function and/or the ana- log comparator function. port configuration is pe r formed by writing to a set of con- trol registers associated with the port. a special-purpose instruction is used to write these control registers: ? mov !ra,w (move w to port a control register) ? mov !rb,w (move w to port b control register) ? mov !rc,w (move w to port c control register) each one of these instructions writes a port control regis- ter for port a, port b, or port c. there are multiple control registers for each port. to specify which one you want to access, you use another register called the mode regis- ter. 3.2.1 mode register the mode register controls access to the port configura- tion registers. because the mode register is not mem- ory-mapped, it is accessed by the following special- purpose instructions: ? mov m, #lit (move literal to mode register) ? mov m,w (move w to mode register) ? mov w,m (move mode register to w) the value contained in the mode register determines which port control register is accessed by the ?mov !rx,w? instruction as indicated in table3-3. mode register val- ues not listed in the table are reserved for future expan- sion and should not be used. therefore, the mode register should always contain a value from 08h to 0fh. upon reset, the mode register is initialized to 0fh, which enables access to the port direction registers. after a value is written to the mode register, that setting remains in effect until it is changed by writing to the mode register again. for example, you can write the value 0eh to the mode register just once, and then write to each of the three pullup configuration registers using the three ?mov !rx,w? instructions. the following code example shows how to program the pullup control registers. first the mode register is loaded with 0eh to select access to the pullup control registers (plp_a, plp_b, and plp_c). then the mov !rx,w instructions are used to specify which port pins are to be connected to the internal pullup resistors. setting a bit to 1 disconnects the corresponding pullup resistor, and clearing a bit to 0 con- nects the corresponding pullup resistor. 3.2.2 port configuration registers the port configuration registers that you control with the mov !rx,w instruction operate as described below. ra, rb, and rc data direction registers (mode=0fh) each register bit sets the data direction for one port pin. set the bit to 1 to make the pin operate as a high-imped- ance input. clear the bit to 0 to make the pin operate as an output. plp_a, plp_b, and plp_c: pullup enable registers (mode=0eh) each register bit determines whether an internal pullup resistor is connected to the pin. set the bit to 1 to discon- nect the pullup resistor or clear the bit to 0 to connect the pullup resistor. table3-3. mode register and port control register access mode reg. mov !ra,w mov !rb,w mov !rc,w 08h not used cmp_b not used 09h not used wkpnd_b not used 0ah not used wked_b not used 0bh not used wken_b not used 0ch not used st_b st_c 0dh lvl_a lvl_b lvl_c 0eh plp_a plp_b plp_c 0fh ra direction rb direction rc direction mov m,#$0e ;mode=0eh to access port pullup ;registers mov w,#$03 ;w = 0000 0011 mov !ra,w ;disable pullups for a0 and a1 mov w,#$ff ;w = 1111 1111 mov !rb,w ;disable all pullups for b0-b7 mov w,#$00 ;w = 0000 0000 mov !rc,w ;enable all pullups for c0-c7
? 1999 scenix semiconductor, inc. all rights reserved. - 9 - www.scenix.com sx18ac / sx20ac / sx28ac lvl_a, lvl_b, and lvl_c: input level registers (mode=0dh) each register bit determines the voltage levels sensed on the input port, either ttl or cmos, when the schmitt trigger option is disabled. program each bit according to the type of device that is driving the port input pin. set the bit to 1 for ttl or clear the bit to 0 for cmos. st_b and st_c: schmitt trigger enable registers (mode=0ch) each register bit determines whether the port input pin operates with a schmitt trigger. set the bit to 1 to disable schmitt trigger operation and sense either ttl or cmos voltage levels; or clear the bit to 0 to enable schmitt trig- ger operation. wken_b: wakeup enable register (mode=0bh) each register bit enables or disables the multi-input wakeup/interrupt (miwu) function for the corresponding port b input pin. clear the bit to 0 to enable miwu opera- tion or set the bit to 1 to disable miwu operation. for more information on using the multi-input wakeup/inter- rupt function, see section 7. 0 . wked_b: wakeup edge register (mode=0ah) each register bit selects the edge sensitivity of the port b input pin for miwu operation. clear the bit to 0 to sense rising (low-to-high) edges. set the bit to 1 to sense falling (high-to-low) edges. wkpnd_b: wakeup pending bit register (mode=09h) when you access the wkpnd_b register using mov !rb,w, the cpu does an exchange between the con- tents of w and wkpnd_b. this feature lets you read the wkpnd_b register contents. each bit indicates the sta- tus of the corresponding miwu pin. a bit set to 1 indi- cates that a valid edge has occurred on the corresponding miwu pin, triggering a wakeup or inter- rupt. a bit set to 0 indicates that no valid edge has occurred on the miwu pin. cmp_b: comparator register (mode=08h) when you access the cmp_b register using mov !rb,w, the cpu does an exchange between the con- tents of w and cmp_b. this feature lets you read the cmp_b register contents. clear bit 7 to enable operation of the comparator. clear bit 6 to place the comparator result on the rb0 pin. bit 0 is a result bit that is set to 1 when the voltage on rb2 is greater than rb1, or cleared to 0 otherwise. (for more information using the compara- tor, see section 11.0.) 3.2.3 port configuration upon reset upon reset, all the port control registers are initialized to ffh. thus, each pin is configured to operate as a high- impedance input that senses ttl voltage levels, with no internal pullup resistor connected. the mode register is initialized to 0fh, which allows immediate access to the data direction registers using the ?mov !rx,w? instruction.
? 1999 scenix semiconductor, inc. all rights reserved. - 10 - www.scenix.com sx18ac / sx20ac / sx28ac 4.0 special-function registers the cpu uses a set of s pecial -f unction registers to con- trol the operation of the device. t he cpu registers include an 8-bit working register (w) , which serves as a pseudo accumulator . it h olds the sec- ond operand of an instruction, receives the literal in i mmediate type instructions, and also can be program - s elected as the destination register. a set o f 31 file registers serve s a s the primary accumula- tor . one of these registers holds t he first operand of an instruction a nd another can b e program -s elected as the destination register. the first eight file registers include the real-time clock/counter register (rtcc), the lower eight bits of the 11-bit program counter (pc), the 8-bit status register, three port control registers for port a, port b, port c, the 8-bit file select register (fsr) , and indf used for indirect addressing . the five low -o rder b its of the fsr register select one of the 31 file register s in the indirect addressing mode. call- ing for the file register located at address 00h (indf) in any of the file -o riented instructions selects indirect addressing , which uses t he fsr register. it should be noted that the file register at address 00h is not a physi- cally implemented register. the cpu also contains an 8- l evel , 11-bit hardware push/pop stack for subroutine link- age. *in the sx18 package, port c is not used, and address 07h is available as a general-purpose ram location. 4.1pc register (02h) the pc register holds the lower eight bits of the program counter. it is accessible at run time to perform branch operations. 4.2status register (03h) the status register holds the arithmetic status of the alu, the page select bits, and the reset state. the status register is accessible during run time, except that bits pd and to are read-only. it is recommended that only setb and clrb instructions be used on this register. care should be exercised when writing to the status register as the alu status bits are updated upon completion of the write operation, possibly leaving the status register with a result that is different than intended. table4-1. special -f unction registers addr name function 00h indf used for indirect addressing 01h rtcc real time clock/counter 02h pc program counter (low byte) 03h status holds status bits of alu 04h fsr file select register 05h ra port ra control register 06h rb port rb control register 07h rc* port rc control register pa2 pa1 pa0 to pd z dc c bit 7 bit 0 bit 7-5: page select bits pa2:pa0 000 = page 0 (000h ? 01ffh) 001 = page 1 (200h ? 03ffh) 010 = page 2 (400h ? 05ffh) 011 = page 3 (600h ? 07ffh) bit 4: time out bit, to 1 = set to 1 a fter power up and u pon exe- cution of clrwdt or sleep instructions 0 = a watchdog time-out occurred bit 3: power down bit, pd 1= set to a 1 a fter power up and u pon ex- ecution of the clrwdt instruction 0 = cleared t o a ?0? upon execution of sleep instruction bit 2: zero bit, z 1 = result of math operation is zero 0 = result of math operation is non-zero bit 1: digit carry bit, dc after addition: 1 = a carry from bit 3 occurred 0 = no carry from bit 3 occurred after subtraction: 1 = no borrow from bit 3 occurred 0 = a borrow from bit 3 occurred bit 0: carry bit, c after addition: 1 = a carry from bit 7 of the result occured 0 = no carry from bit 7 of the result oc- cured after substraction: 1 = no borrow from bit 7 of the result oc- cured 0 = a borrow from bit 7 of the result oc- cured rotate (rr or rl) instructions: the carry bit is loaded with the low or high order bit, respectively. when cf bit is cleared, carry bit works as input for add and sub instructions.
? 1999 scenix semiconductor, inc. all rights reserved. - 11 - www.scenix.com sx18ac / sx20ac / sx28ac 4.3optionregister when the optionx bit in the fuse word is cleared, bits 7 and 6 of the option register function as described below . when the optionx bit is set, bits 7 and 6 of the option register read as ?1?s. upon reset, all bits in the option register are set to 1. rtw rte _ie rts rte _es psa ps2 ps1 ps0 bit 7 bit 0 rtw rtcc/w register selection: 0 = register 01h addresses w 1 = register 01h addresses rtcc rte_ie rtcc edge interrupt enable: 0 = rtcc roll-over interrupt is enabled 1 = rtcc roll-over interrupt is disabled rts rtcc increment select: 0 = rtcc increments on internal instruction cycle 1 = rtcc increments upon transition on rtcc pin rte_es rtcc edge select: 0 = rtcc increments on low-to-high transi- tions 1 = rtcc increments on high-to- l ow transi- tion s psa prescaler assignment: 0 = prescaler is assigned to rtcc, with di- vide rate determined by ps0-ps2 bits 1 = prescaler is assigned to wdt, and divide rate on rtcc is 1:1 ps2-ps0 prescaler divider (see table4-2) table4-2. prescaler divider ratios ps2, ps1, ps0 rtcc divide rate watchdog timer divide rate 000 1 :2 1 :1 001 1 :4 1 :2 010 1 :8 1 :4 011 1 :16 1 :8 100 1 :32 1 :16 101 1 :64 1 :32 110 1 :128 1 :64 111 1 :256 1 :128
? 1999 scenix semiconductor, inc. all rights reserved. - 12 - www.scenix.com sx18ac / sx20ac / sx28ac 5.0device configuration registers the sx device has three registers (fuse, fusex, device) that control functions such as operating the device in turbo mode, extended (8-level deep) stack operation, and speed selection for the internal rc oscilla- tor. these registers are not programmable ?on the fly? during normal device operation. instead, the fuse and fusex registers can only be accessed when the sx device is being programmed. the device register is a read-only, hard-wired register, programmed during the manufacturing process. 5.1fuse word (read/program at fffh in main memory map) turbo sync reserved reserved irc div1/ ifbd div0/ fosc2 res- rved cp wdte fosc1 fosc0 bit 11 bit 0 turbo turbo mode enable: 0 = turbo (instr uction clock = osc/1) 1 = instr clock = osc/4 sync synchronous input enable (for turbo mode): this bit synchronizes the signal presented at the input pin to the internal clock through two internal flip-flops. 0 = enabled 1 = disabled irc internal rc oscillator enable: 0 = enabled - osc1 pulled low by weak pullup, osc2 pulled high by weak pullup 1 = disabled - osc1 and osc2 behave according to fosc2: fosc0 div2: div0 internal rc oscillator divider: 00b = 4 mhz 01b = 1 mhz 10 = 128 khz 11b = 32 khz ifbd internal crystal/resonator oscillator feedback resistor: 0= disabled internal feedback resistor disable (external feedback required) 1= enabled internal feedback resistor enabled ( valid when irc = 1) cp code protect enable: 0 = enabled (fuse, co de , and id memories read back as garbled data) 1 = disabled (fuse, code, and id memories can be read normally) wdte w atchdog timer enable: 0 = disabled 1 = enabled fosc2: fosc0 external oscillator configuration (valid when irc = 1): 000b = lp1 ? low power crystal (32khz) 001b = lp2 ? low power crystal (32 khz to 1 mhz) 010b = xt1 ? normal crystal (32 khz to 10 mhz) 011b = xt2 ? normal crystal (1mhz to 24 mhz) 100b = hs ? high speed crystal (1mhz to 50 mhz) 101b = reserved 110b = reserved 111b = rc network - osc2 is pulled high with a weak pullup (no clkout output) note: the frequencies are target values.
? 1999 scenix semiconductor, inc. all rights reserved. - 13 - www.scenix.com sx18ac / sx20ac / sx28ac 5.2fusex word (read/program via programming command) 5.3device word (hard-wired read-only) irctri m2 pins irctri m1 irctri m0 optionx / stackx cf bor1 bor0 bortri m1 bortri m2 bp1 bp0 bit 11 bit 0 irctrim2: irctrim0 internal rc oscillator trim bits. this 3-bit field adjusts the operation of the internal rc oscillator to make it operate within the target frequency range 4 mhz plus or minus 8%. parts are shipped from the factory untrimmed. the device relies on the programming toll to provide the trimming function. 000b = minimum frequency 111b = maximum frequency each step about 3% pins selects the number of pins. optionx/ stackx option register extension and stack extension. set to 1 to disable the programmability of bit 6 and bit 7 in the option register, the rtw and rte_ie bits (in other words, to force these two bits to 1); and to limit the program stack size to two locations. clear to 0 to enable programming of the rtw and rte_ie bits in the option register, and to extend the stack size to eight locations. cf active low ? makes carry bit input to add and sub instructions. bor1: bor0 brown-out reset;these bits enable or disable the brown-out reset function and set the brown-out threshold voltage as foolows: 00b = 4.2v 01b = 2.6v 10b = 2.2v 11b = brown-out disabled bortrim1: bortrim2 brown-out trim bits (parts are shipped out of factory untrimmed). bp1:bp0 configure memory size: 00b = 1 page, 1 bank 01b = 1 page, 2 banks 10b = 4 pages, 4 banks 11b = 4 pages, 8 banks (default configuration ) 1 1 1 1 1 1 0 0 1 1 1 0 bit 11 bit 0
? 1999 scenix semiconductor, inc. all rights reserved. - 14 - www.scenix.com sx18ac / sx20ac / sx28ac 6.0memory organization 6.1program memory the program memory is organized as 2k, 12-bit wide words. the program memory words are addressed sequentially by a binary program counter. the program counter starts at zero. if there is no branch operation, it will increment to the maximum value possible for the device and roll over and begin again. internally, the program memory has a semi-transparent page structure. a page is composed of 512 contiguous program memory words. the lower nine bits of the pro- gram counter are zeros at the first address of a page and ones at the last address of a page. this page structure has no effect on the program counter. the program counter will freely increment through the page bound- aries. 6.1.1 program counter the program counter contains the 11-bit address of the instruction to be executed. the lower eight bits of the pro- gram counter are contained in the pc register (02h) while the upper bits come from the upper three bits of the sta- tus register (pa0, pa1, pa2). this is necessary to cause jumps and subroutine calls across program mem- ory page boundaries. prior to the execution of a branch operation, the user program must initialize the upper bits of the status register to cause a branch to the desired page. an alternative method is to use the page instruc- tion, which automatically causes branch to the desired page, based on the value specified in the operand field. upon reset, the program counter is initialized with 07ffh. 6.1.2 subroutine stack the subroutine stack consists of eight 11-bit save regis- ters. a physical transfer of register contents from the pro- gram counter to the stack or vice versa, and within the stack, occurs on all operations affecting the stack, prima- rily calls and returns. the stack is physically and logically separate from data ram. the program cannot read or write the stack. 6.2data memory the data memory consists of 136 bytes of ram, orga- nized as eight banks of 16 registers plus eight registers which are not banked. both banked and non-banked memory locations can be addressed directly or indirectly using the fsr (file select register). the special-func- tion registers are mapped into the data memory. 6.2.1 file select register (04h) instructions that specify a register as the operand can only express five bits of register address. this means that only registers 00h to 1fh can be accessed. the file select register (fsr) provides the ability to access reg- isters beyond 1fh. figure6-1 shows how fsr can be used to address ram locations. the three high-order bits of fsr select one of eight sram banks to be accessed. the five low-order bits select one of 32 sram locations within the selected bank. for the lower 16 addresses, bank 0 is always accessed, irrespective of the three high-order bits. thus, ram register addresses 00h through 0fh are ?global? in that they can always be accessed, regardless of the con- tents of the fsr. the entire data memory (including the dedicated-function registers) consists of the lower 16 bytes of bank 0 and the upper 16 bytes of bank 0 through bank 7, for a total of (1+8)*16 = 144 bytes. eight of these bytes are for the function registers, leaving 136 general-purpose memory locations. in the 18-pin sx packages, register rc is not used, which makes address 07h available as an addi- tional general-purpose memory location. below is an example of how to write to register 10h in bank 4: mov fsr,#$90 ;select bank 4 by ;setting fsr<7:5> mov $10,#$64 ;load register 10h with ;the literal 64h
? 1999 scenix semiconductor, inc. all rights reserved. - 15 - www.scenix.com sx18ac / sx20ac / sx28ac figure6-1. data memory organization function registers indf rtcc pc status fsr ra rb rc sram (8 bytes) bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 bank 0 30 50 70 90 b0 d0 f0 3f 5f 7f 9f bf df ff 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 00 07 0f 10 1f fsr sram (16 bytes each bank 128 bytes total) 7 6 5 4 3 2 1 0 bank 0 is always accessed for the lower 16 addresses, irrespective of the three high- order bits of fsr. registers (8 bytes) bank 0
? 1999 scenix semiconductor, inc. all rights reserved. - 16 - www.scenix.com sx18ac / sx20ac / sx28ac 7.0 power down mode the power down mode is entered by executing the sleep instruction. in power down mode, only the watchdog timer (wdt) is active. if the watchdog timer is enabled, upon execution of the sleep instruction, the watchdog timer is cleared, the to (time out) bit is set in the status register, and the pd (power down) bit is cleared in the status regis- ter. there are three different ways to exit from the power down mode: a timer overflow signal from the watchdog timer (wdt), a valid transition on any of the multi-input wakeup pins (port b pins), or through an external reset input on the mclr pin. to achieve the lowest possible power consumption, the watchdog timer should be disabled and the device should exit the power down mode through the multi-input wakeup (miwu) pins or an external reset. 7.1multi-input wakeup multi-input wakeup is one way of causing the device to exit the power down mode. port b is used to support this feature. the wken_b register (wakeup enable regis- ter) allows any port b pin or combination of pins to cause the wakeup. clearing a bit in the wken_b register enables the wakeup on the corresponding port b pin. if multi-input wakeup is selected to cause a wakeup, the trigger condition on the selected pin can be either rising edge (low to high) or falling edge (high to low). the wked_b register (wakeup edge select) selects the desired transition edge. setting a bit in the wked_b reg- ister selects the falling edge on the corresponding port b. clearing the bit selects the rising edge. the wken_b and wked_b registers are set to ffh upon reset. once a valid transition occurs on the selected pin, the wkpnd_b register (wakeup pending register) latches the transition in the corresponding bit position. a logic ?1? indicates the occurrence of the selected trigger edge on the corresponding port b pin. upon exiting the power down mode, the multi-input wakeup logic causes program counter to branch to the maximum program memory address (same as reset). figure7-1 shows the multi-input wakeup block diagram. figure7-1. multi-input wakeup block diagram w i n t e r n a l d a t a b u s mode wake-up : exit power down 8 8 rb7 rb6 rb1 rb0 wked_b wkpnd_b wken_b mode = 09 m o d e = 0 b m o d e = 0 a port b configured as input 0 1 8 0 = enable 1 = disable
? 1999 scenix semiconductor, inc. all rights reserved. - 17 - www.scenix.com sx18ac / sx20ac / sx28ac 7.2port b miwu/interrupt configuration t he wkpnd_b register comes up with a random value upon reset. the user program must clear the register prior to enabling the wake-up condition or interrupts . the proper initialization sequence is: 1. select the desired edge (through wked_b register) 2. clear the wkpnd_b register 3. enable the wakeup condition (through wken_b regis- ter) below is an example of how to read the wkpnd_b regis- ter to determine which port b pin caused the wakeup or interrupt, and to clear the wkpnd_b register: the final ?mov? instruction in this example performs an exchange of data between the working register (w) and the wkpnd_b register. this exchange occurs only with port b accesses. otherwise, the ?mov? instruction does not perform an exchange, but only moves data from the source to the destination. here is an example of a program segment that config- ures the rb0, rb1, and rb2 pins to operate as multi- input wakeup/interrupt pins, sensitive to falling edges: to prevent false interrupts, the enabling step (clearing bits in wken_b) should be done as the last step in a sequence of port b configuration steps. after this pro- gram segment is executed, the device can receive inter- rupts on the rb0, rb1, and rb2 pins. if the device is put into the power down mode (by executing the sleep instruction), the device can then receive wakeup signals on those same pins. mov m,#$09 clr w mov !rb,w ;w contains wkpnd_b ;contents of w exchanged ;with contents of wkpnd_b mov m,#$0f ;prepare to write port data ;direction registers mov w,#$07 ;load w with the value 07h mov !rb,w ;configure rb0-rb2 to be inputs mov m,#$0a ;prepare to write wked_b ;(edge) register ;w contains the value 07h mov !rb,w ;configure rb0-rb2 to sense ;falling edges mov m,#$09 ;prepare to access wkpnd_b ;(pending) register mov w,#$00 ;clear w mov !rb,w ;clear all wakeup pending bits mov m,#$0b ;prepare to write wken_b (enable) ;register mov w,#$f8h ;load w with the value f8h mov !rb,w ;enable rb0-rb2 to operate as ;wakeup inputs
? 1999 scenix semiconductor, inc. all rights reserved. - 18 - www.scenix.com sx18ac / sx20ac / sx28ac 8.0interrupt support the device supports both internal and external maskable interrupts. the internal interrupt is generated as a result of the rtcc rolling over from 0ffh to 00h. this interrupt source has an associated enable bit located in the option register. there is no pending bit associated with this interrupt. port b provides the source for eight external software selectable, edge sensitive interrupts. these interrupt sources share logic with the multi-input wakeup circuitry. the wken_b register allows interrupt from port b to be individually enabled or disabled. clearing a bit in the wken_b register enables the interrupt on the corre- sponding port b pin. the wked_b selects the transition edge to be either positive or negative. the wken_b and wked_b registers are set to ffh upon reset. setting a bit in the wked_b register selects the falling edge while clearing the bit selects the rising edge on the correspond- ing port b pin. the wkpnd_b register serves as the external interrupt pending register. t he wkpnd_b register comes up a with random value upon reset. the user program must clear the wkpnd_b register prior to enabling the interrupt. the proper sequence is described in section 7.2. figure8-1 shows the structure of the interrupt logic. figure8-1. interrupt structure rtcc wked_b i n t e r n a l d a t a b u s wked_b wkpnd_b wkpnd_b from mode (mode = 09) option rte_ie wken_b 1 = ext. interrupt through port b 0 = power down mode, no ext. interrupt status port b pin interrupt pc interrupt stack pc 000 overflow register pd bit from mode (mode = 0a)
? 1999 scenix semiconductor, inc. all rights reserved. - 19 - www.scenix.com sx18ac / sx20ac / sx28ac all interrupts are global in nature; that is, no interrupt has priority over another. interrupts are handled sequentially. figure8-2 shows the interrupt processing sequence. once an interrupt is acknowledged, all subsequent global interrupts are disabled until return from servicing the cur- rent interrupt. the pc is pushed onto the single level interrupt stack, and the contents of the fsr, status, and w registers are saved in their corresponding shadow registers. the status bits pa0, pa1, and pa2 bits are c leared after the status register has been saved in its shadow register. the interrupt logic has its own single- level stack and is not part of the call subroutine stack. the vector for the interrupt service routine is address 0. once in the interrupt service routine, the user program must check all external interrupt pending bits (contained in the wkpnd_b register) to determine the source of the interrupt. the interrupt service routine should clear the corresponding interrupt pending bit . if both internal and external interrupts are enabled, the user program may also need to read the contents of rtcc to determine any recent rtcc rollover. this is needed since there is no interrupt pending bit associated with the rtcc rollover. normally it is a requirement for the user program to pro- cess every interrupt without missing any. to ensure this, the longest path through the interrupt routine must take less time than the shortest possible delay between inter- rupts. if an external interrupt occurs during the interrupt routine, the pending register will be updated but the trigger will be ignored unless interrupts are disabled at the beginning of the interrupt routine and enabled again at the end. this also requires that the new interrupt does not occur before interrupts are disabled in the interrupt routine. if there is a possibility of additional interrupts occuring before they can be disabled, the device will miss those interrupt trig- gers. in other words, using more than one interrupt, such as multiple external interrupts or both rtcc and external interrupts, can result in missed or, at best, jittery interrupt handling should one occur during the processing of another. when handling external interrupts, the interrupt routine should clear at least one pending register bit. the bit that is cleared should represent the interrupt being handled in order for the next interrupt to trigger. upon return from the interrupt service routine, the con- tents of pc, fsr, status, and w registers are restored from their corresponding shadow registers. the interrupt service routine should end with instructions such as reti and retiw. reti pops the interrupt stack and the spe- cial shadow registers used for storing w, status, and fsr (preserved during interrupt handling). retiw behaves like reti but also adds w to rtcc. the inter- rupt return instruction enables the global interrupts. figure8-2. interrupt processing interrupt pc reti pc pc w register 000h address 000h program memory interrupt service routine status register fsr register w shadow register status shadow register fsr shadow register w register status register fsr register w shadow register status shadow register fsr shadow register stack interrupt stack note: the interrupt logic has its own single-level stack and is not part of the call subroutine stack.
? 1999 scenix semiconductor, inc. all rights reserved. - 20 - www.scenix.com sx18ac / sx20ac / sx28ac 9.0oscillator circuits the device supports several user -s electable oscillator modes. the oscillator modes are selected by program- ming the appropriate values into the fuse word register. these are the d ifferent oscillator modes offered: 9.1xt, lp or hs modes in xt, lp or hs , modes, you can use either an external resonator network or an external clock signal as the device clock. to use an external resonator network, you connect a crystal or ceramic resonator t o the osc1/clkin and osc2/clkout pins according to the circuit configura- tion shown in figure9-1. a p arallel resonant crystal type is recommended . use of a series resonant crystal may result in a frequency that is outside the crystal manufac- turer specifications. bits 0, 1 and 5 of the fuse register (fosc1:fosc2) are used to configure the diffrent external resonator/crystal oscillator modes. these bits allow the selection of the appropriate gain setting for the internal driver to match the desired operating frequency. if t he xt, lp , or hs mode is s elected, the osc1/clkin pin can be driven by an external clock source rather than a resonator network, as long as the clock signal m eets the specified duty cycle, rise and fall times, and input levels (figure9-2). in this case, the osc2/clkout pin should be left open. the recommended target values for the external component values are available at scenix website.. 9.2external rc mode th e external rc o scillator mode provides a cost -e ffective approach for a pplications that do not require a precise operating frequency. in this mode, the rc oscillator fre- quency is a function of the supply voltage, the resistor (r) and capacitor (c) values, and the operating temperature. in addition, the oscillator frequency will vary from unit to unit due to normal manufacturing process variations. fur- thermore, the difference in lead frame capacitance between package types a lso affect s the oscillation fre- quency, especially for low c values. the external r and c component tolerances contribute to oscillator fre- quency variation as well. figure9-3 shows the external rc connection diagram. the recommended r value is from 3k w to 100k w . for r values below 2.2k w , the oscillator m ay become unstable, or may stop completely. for very high r values ( such as 1 m w ) , the oscillator becomes sensitive to noise, humid- ity , and leakage. although the oscillator will operate with no external capacitor (c = 0pf), it is recommended that you u se val- ues above 20 pf for noise immunity and stability . with no or small external capacitance, the oscillation frequency can vary significantly due to variation in pcb trace or package lead frame capacitances. in the external rc mode, the osc2/clkout pin pro- vides an output frequency, which the input frequency divided by four. 9.3internal rc mode th e internal rc m ode uses an internal o scillator , so the d evice does not need a ny external components. at 4 mhz, the internal oscillator provides +/ ?8 % accuracy over the allowed temperature range . the internal clock frequency can be divided down to provide one of eight lower -f requency choices by selecting the desired value in the fuse word register. the frequency range is from 31.25 khz to 4 mhz. the default operating frequency of the internal rc oscillator may not be 4 mhz. this is due lp: low power crystal xt: crystal/resonator hs: high speed crystal/resonator rc: external resistor/capacitor internal resistor/capacitor figure9-1. crystal operation (or ceramic resonator) (hs, xt or lp osc configuration) sx device rf xtal osc2 osc1 c 1 c 2 internal circuitry sleep rs figure9-2. external clock input operation (hs, xt or lp osc configuration) externally generated clock osc1 osc2 open sx device
? 1999 scenix semiconductor, inc. all rights reserved. - 21 - www.scenix.com sx18ac / sx20ac / sx28ac to the fact that the sx device requires trimmimg to obtain 4 mhz operation. the parts shipped out of the factory are not trimmed. the device relies on the programming tool provided by the third party vendors to support trimmimg. 10.0real time clock (rtcc)/watchdog timer the device contain s an 8-bit real time clock /counter (rtcc) and an 8-bit watchdog timer ( wdt). an 8-bit programmable prescaler extends the rtcc to 16 b it s . if the prescaler is not used for the rtcc, it can serve as a postscaler for the watchdog timer. figure10-1 shows the rtcc and wdt block diagram. 10.1rtcc rtcc is an 8-bit real-time timer that is incremented once each instruction cycle or from a transition on the rtcc pin. the on-board prescaler can be used to extend the rtcc counter to 16 bits. the rtcc counter can be clock ed by the internal instruc- tion cycle clock or by an external clock source presented at the rtcc pin. t o select the internal clock source, bit 5 of the option register should be cleared. in this mode, rtcc is incre- mented a t each instruction cycle unless the prescaler is selected to increment the counter. to select the external clock source, bit 5 of the option register must be set. in this mode, the rtcc counter is incremented w ith each valid signal transition at the rttc pin. by using bit 4 of the option register, the transition can be programmed to be either a falling edge or rising edge. setting the control bit s elect s the falling edge to increment the counter. clearing the bit selects the rising edge. the rtcc generates an interrupt as a result of an rtcc roll o ver from 0ff to 000. there is no interrupt pending bit to indicate the overflow occurrence. the rtcc register must be s ampled by the program to determine any over- flow occurrence. 10.2watchdog timer the watchdog logic consists of a watchdog timer which shares the same 8-bit programmable prescaler with the rtcc. the prescaler actually serves as a postscaler if used in conjunction with the wdt, in contrast to its use as a prescaler with the rtcc. 10.3the prescaler the 8-bit prescaler may be assigned to either the rtcc or the wdt through the psa bit (bit 3 of the option r eg- ister). setting the psa bit assigns the prescaler to the wdt. if assigned to the wdt, the wdt clocks the pres- caler and the prescaler divide rate is selected by the ps 0, ps1, and ps2 bits located in the option register. clearing the psa bit assigns the prescaler to the rtcc. once assigned to the rtcc, the prescaler clocks the rtcc and the divide rate is selected by the ps0, ps1, and ps2 bits i n the option register. the prescaler is not mapped into the data memory, so run - time access is not possible. the prescaler cannot be assigned to both the rtcc and wdt simultaneously. figure9-3. rc oscillator mode v dd r c internal circuitry osc2 osc1 n ? 4 ~ ~ sx device figure10-1. rtcc and wdt block diagram wdte (from fuse word) rtcc pin mux 8-bit prescaler mux (8 to 1) 8-bits wdt time-out data bus wdt mux m rtcc m u x f osc rst rte_es psa ps2 ps1 ps0 option register rtcc rollover interrupt rte_ie rtw rtcc interrupt enable u x
? 1999 scenix semiconductor, inc. all rights reserved. - 22 - www.scenix.com sx18ac / sx20ac / sx28ac 11.0comparator the device contains an on-chip differential comparator. ports rb0-rb2 support the comparator . p orts rb1 and rb2 are the comparator negative and positive inputs , respectively, while port rb0 serves as the comparator output pin. to use these pins in conjunction with the com- parator, the user program must configure ports rb1 and rb2 as inputs and port rb0 as an output. the cmp_b register is used to enable the comparator, to read the output of the comparator internally, and to enable the out- put of the comparator to the comparator output pin. the comparator enable bits are set to ?1? upon reset, thus disabling the comparator. to avoid drawing addi- tional current during the power down mode, the compara- tor should be disabled before entering the pwer down mode. here is an example of how to setup the compara- tor and read the cmp_b register . the final ?mov? instruction in this example performs an exchange of data between the working register (w) and the cmp_b register. this exchange occurs only with port b accesses. otherwise, the ?mov? instruction does not perform an exchange, but only moves data from the source to the destination. f gure 11-1 shows the comparator block diagram . cmp_b - comparator enable/status register mov m,#$08 ;set mode register to access ;cmp_b mov w,#$00 ;clear w mov !rb,w ;enable comparator and its ;output ... ;delay after enabling ;comparator for response mov m,#$08 ;set mode register to access ;cmp_b mov w,#$00 ;clear w mov !rb,w ;enable comparator and its ;output and also read cmp_b ;(exchange w and cmb_b) and w,#$01 ;set/clear z bit based on ;comparator result snb $03.2 ;test z bit in status reg ;(0 => rb2rb1 ... cmp_en cmp_oe reserved cmp_res bit 7 bit 6 bits 5?1 bit 0 cmp_res comparator result: 1 for rb2>rb1 or 0 for rb2 ? 1999 scenix semiconductor, inc. all rights reserved. - 23 - www.scenix.com sx18ac / sx20ac / sx28ac figure11-1. comparator block diagram w mode cmp_en cmp_oe r e s e r v e d cmp_res rb0 rb1 rb2 cmp_b mode = 08h point to cmp_b internal data bus 7 6 0 - +
? 1999 scenix semiconductor, inc. all rights reserved. - 24 - www.scenix.com sx18ac / sx20ac / sx28ac 12.0reset power-on-reset, brown -o ut reset, watchdog reset, or external reset initializes the device. each one of these reset conditions causes the program counter to branch to the top of the program memory. for example, on the device with 2048k words of program memory, the pro- gram counter is initialized to 07ff. the device incorporates an on-chip power-on reset (por) circuit that generates an internal reset as v dd rises during power-up. figure12-1 is a block diagram of the circuit. the circuit contains an 10-bit delay reset timer (drt) and a reset latch. the drt controls the reset time- out delay. the reset latch controls the internal reset sig- nal. upon power-up, the reset latch is set (device held in reset), and the drt starts counting once it detects a valid logic high signal at the mclr pin. once drt reaches the end of the timeout period (typically 72 msec), the reset latch is cleared, releasing the device from reset state. figure12-2 shows a power-up sequence where mclr is not tied to the v dd pin and v dd signal is allowed to rise and stabilize before mclr pin is brought high. the device will actually come out of reset t drt msec after mclr goes high. the brown-out circuitry resets the chip when device power (v dd ) dips below its minimum allowed value, but not to zero, and then recovers to the normal value. figure12-3 shows the on-chip power-on reset sequence where the mclr and v dd pins are tied together. the v dd signal is stable before the drt time- out period expires. in this case, the device will receive a proper reset. however, figure12-4 depicts a situation where v dd rises too slowly. in this scenario, the drt will time-out prior to v dd reaching a valid operating voltage level (v dd min). this means the device will come out of reset and start operating with the supply voltage not at a valid level. in this situation, it is recommended that you use the external rc circuit shown in figure12-5. the rc delay should exceed the time period it takes v dd to reach a valid operating voltage. note: ripple counter is 10 bits for power on reset (por) only. figure12-1. block diagram of on- ch ip reset circuit por brown-out miwu mclr /vpp pin wdt_time_out 10-bit asynch ripple counter ( drt start-up timer) v dd rc_clk drt_time _out s r q qn reset por enable figure12-2. time-out sequence on power-up ( mclr not tied to v dd ) v dd mclr por drt_time_out reset tdrt
? 1999 scenix semiconductor, inc. all rights reserved. - 25 - www.scenix.com sx18ac / sx20ac / sx28ac note1: the ex ternal power-on reset circuit is required only if v dd power-up is too slow. the diode d helps dis- charge the capacitor quickly when v dd powers down. note2: r < 40 k w is recommended to make sure that voltage drop across r does not violate the device electri- cal specification s . note3: r1 = 100 w to 1k w will limit any current flowing into mclr from external capacitor c . this helps prevent mclr pin breakdown due to electrostatic discharge (esd) or electrical overstress (eos). 13.0brown-out detector the on-chip brown-out detection circuitry resets the device when v dd dips below the specified brown-out volt- age. the device is held in reset as long as v dd stays below the brown-out voltage. the device will come out of reset when v dd rises above the brown-out voltage. the brown-out level is preset to approximately 4.2v at the factory. the brown-out circuit can be disabled through bor0 and bor1 bits contained in the fusex word reg- ister. figure12-3. time-out sequence on power-up ( mclr tied to v dd ): fast v dd rise time figure12-4. time-out sequence on power-up ( mclr tied to v dd ): slow rise time figure12-5. external power-on reset circuit (for slow v dd p ower-up) v dd mclr por drt_time_out reset tdrt v dd mclr por drt_time_out reset tdrt v1 v dd r c mclr d r1
? 1999 scenix semiconductor, inc. all rights reserved. - 26 - www.scenix.com sx18ac / sx20ac / sx28ac 14.0register states upon different reset operations the effect of different reset operation on a register depends on the register and the type of reset operation. some registers are initialized to specific values, some are left unchanged (for wakeup and brown-out resets), and some are initialized to an unknown value. a register that starts with an unknown value should be initialized by the software to a known value; you cannot simply test the initial state and rely on it starting in that state consistently. table14-1 lists the sx registers and shows the state of each register upon different reset. table14-1. register states upon different resets register power-on wakeup brown-out watchdog timeout mclr w undefined unchanged undefined unchanged unchanged option ffh ffh ffh ffh ffh mode 0fh 0fh 0fh 0fh 0fh rtcc (01h) undefined unchanged undefined unchanged unchanged pc (02h) ffh ffh ffh ffh ffh status (03h) bits 0-2: unde- fined bits 3-4: 11 bits 5-7: 000 bits 0-2: un- changed. bits 3-4: unch. bits 5-7: 000 bits 0-4: unde- fined bits 5-7: 000 bits 0-2: unch- naged bits 3-4: (note 1) bits 5-7: 000 bits 0-2: un- changed bits 3-4: (note 2) bits 5-7: 000 fsr (04h) undefined bits 0-6: un- changed bit 7: 1 bits 0-6: unde- fined bit 7: 1 bits 0-6: un- changed bit 7: 1 bits 0-6: un- changed bit 7: 1 ra/rb/rc direction ffh ffh ffh ffh ffh ra/rb/rc data undefined unchanged undefined unchanged unchanged other file registers - sram undefined unchanged undefined unchanged unchanged cmp_b bits 0, 6-7: 1 bits 1-5: unde- fined bits 0, 6-7: 1 bits 1-5: unde- fined bits 0, 6-7: 1 bits 1-5: unde- fined bits 0, 6-7: 1 bits 1-5: unde- fined bits 0, 6-7: 1 bits 1-5: unde- fined wkpnd_b undefined unchanged undefined unchanged unchanged wked_b ffh ffh ffh ffh ffh wken_b ffh ffh ffh ffh ffh st_b/st_c ffh ffh ffh ffh ffh lvl_a/lvl_b/lvl_c ffh ffh ffh ffh ffh plp_a/plp_b/plp_c ffh ffh ffh ffh ffh watchdog counter undefined unchanged undefined unchanged unchanged note: 1. watchdog reset during power down mode: 00 (to, pd) watchdog reset during active mode: 01 (to, pd) note: 2. external reset during power down mode: 10 (to, pd) external reset during active mode: unchanged (to, pd)
? 1999 scenix semiconductor, inc. all rights reserved. - 27 - www.scenix.com sx18ac / sx20ac / sx28ac 15.0 instruction set as mentioned earlier, the sx family of devices uses a modified harvard architecture with memory -m apped input/output. the device also has a risc type architec- ture in that there are 43 single -w ord basic instructions. the instruction set contains byte-oriented file register, bit- oriented file register, and literal/control instructions. working register w is one of the cpu registers, which serves as a pseudo accumulator. it is a pseudo accumu- lator in a sense that it holds the second operand, receives the literal in the immediate type instructions, and also can be program -s elected as the destination register. the bank of 31 file register s can also serve as the pri- mary accumulators , but they represent the first operand and may be program -s elected as the destination regis- ters. 15.1instruction set features 1. all single -w ord (12-bit) instructions for compact code efficiency. 2. all instructions are single cycle except the jump type in- structions (jmp, call) and failed test instructions (decsz fr, incsz fr, sb bit, snb bit) , which are two - c ycle. 3. a set of file registers can be addressed directly or indi- rectly, and serve as accumulators to provide first oper- and ; w register provides the second operand. 4. many instructions include a destination bit which se- lects either the register file or the accumulator as the destination for the result. 5. bit manipulation instructions (set, clear, test and skip if set, test and skip if clear). 6. status word register memory -m apped as a register file , allowing t esting of status bits (carry, digit carry, ze- ro, power down, and time o ut). 7. program counter (pc) memory -m apped as register file allows w to be used as offset register for indirect ad- dressing of program memory. 8. indirect addressing data pointer fsr (file select regis- ter) memory -m apped as a register file. 9. iread instruction allows reading the instruction from the program memory addressed by w and upper four bits of mode register. 10. eight -l evel , 11-bit push/pop hardware stack for sub- routine linkage using the ca ll and re turn instructions. 11. six addressing modes provide great flexibility. 15.2instruction execution an instruction goes through a four-stage pipeline to be executed (figure15-1). the first instruction is fetched from the program memory on the first clock cycle. on the second clock cycle, the first instruction is decoded and the second instruction is fetched. on the third clock cycle, the first instruction is executed, the second instruction is decoded, and the third instruction is fetched. on the fourth clock cycle, the first instruction?s results are written to its destination, the second instruction is executed, the third instruction is decoded, and the fourth instruction is fetched. once the pipeline is full, instructions are exe- cuted at the rate of one per clock cycle. instructions that directly affect the contents of the pro- gram counter (such as jumps and calls) require that the pipeline be cleared and subsequently refilled. therefore, these instruction take more than one clock cycle. the instruction execution time is derived by dividing the oscillator frequency by either one (turbo mode) or four (non-turbo mode). the divide-by factor is selected through the fuse word register. 15.3addressing modes the device support the following addressing modes: data direct data indirect immediate program direct program indirect relative both direct and indirect addressing modes are available. the indf register, though physically not implemented, is used in conjunction with the indirect data pointer (fsr) to perform indirect addressing. an instruction using indf as its operand field a ctually performs the operation on the register pointed by the contents of the fsr. conse- quently, processing two multiple -b yte operands require s alternate loading of the operand addresses into the fsr pointer as the multiple byte data fields are processed. examples: direct addressing: indirect addressing: figure15-1. pipeline and clock scheme mov ra,#01 ;move ?1? to ra mov fsr,#ra ;fsr = address of ra mov indf,#$01 ;move ?1? to ra fetch decode execute write clock cycle 1 clock cycle 2 clock cycle 3 clock cycle 4
? 1999 scenix semiconductor, inc. all rights reserved. - 28 - www.scenix.com sx18ac / sx20ac / sx28ac 15.4ram addressing direct addressing the fsr register must initialized with an appropriate value in order to address the desired ram register. the following table and code example s how how to directly access the banked registers. indirect addressing to access any register via indirect addressing, simply move the eight-bit address of the desired register into the fsr and use indf as the operand. the example below shows how to clear all ram locations from 10h to 1fh in all eight banks: 15.5the bank instruction often it is desirable to set the bank select bits of the fsr register in o ne instruction cycle. the bank instruction provides this capability. this instruction sets the upper bits of the fsr to point to a specific r am bank without affecting the other fsr bits. example: 15.6bit manipulation the instruction set contains instructions to set, reset, and test individual bits in data memory. the device is capable of bit addressing anywhere in data memory . 15.7input/output operation the device contains three registers associated with each i/o port. the first register (data direction register), con- figures each port pin as a hi-z input or output. the sec- ond register (ttl/cmos register), selects the desired input level for the input. the third register (pull -up regis- ter), enables a weak pull-up resistor on the pin configured as a input. in addition to using the associated port regis- ters, appropriate values must be written into the mode register t o configure the i/o ports. when two successive read-modify-write instructions are used on the same i/o port with a very high clock rate, the ?write? part of one instruction might not occur soon enough before the ?read? part of the very next instruction, resulting in getting ?old? data for the second instruction. to ensure predictable results, avoid using two succes- sive read-modify-write instructions that access the same port data register if the clock rate is high. 15.8increment/decrement the bank of 31 register s s erves as a set of a ccumulators. the instruction set contains instructions to increment and decrement the register file. the device also includes both incsz fr (increment file register and skip if zero) and decsz fr (decrement file register and skip if zero) instructions. 15.9loop counting and data pointing testing the device has specific instructions to facilitate loop counting. the decsz fr (decrement file register and skip if zero) tests any one of the file registers and skips the next instruction ( which can be a branch back to loop) if the result is zero. 15.10branch and loop call instructions the device contains an 8-l evel hardware stack where the return address is stored with a subroutine call. multiple stack levels allow subroutine nesting. the instruction set supports absolute address branching. 15.10.1 jump operation when a jmp instruction is executed , the lower nine bits of the program counter is loaded with the address of the specified label . the upper two bits of the program counter are loaded with the page select bits, pa1:pa0, contained in the status register. therefore, care must be exercised to ensure the page select bits are pointing to the correct page before the jump occurs. 15.10.2 page jump operation when a jmp instruction is executed and the intended destination is on a different page, the page select bits bank fsr value 0 010h 1 030h 2 050h 3 070h 4 090h 5 0b0h 6 0d0h 7 0f0h mov fsr,#$070 ;select ram bank 3 clr $010 ;clear register 10h on ;bank 3 mov fsr,#$d0 ;select ram bank 6 clr $010 ;clear register 10h on ;bank 6 clr fsr ;clear fsr to 00h (at address ;04h) :loop setb sfr.4 ;set bit 4: address 10h-1fh, ;30-3fh, etc clr indf ;clear register pointed to by ;fsr incsz fsr ;increment fsr and test, skip ;jmp if 00h jmp :loop ;jump back and clear next ;register bank $f0 ;select bank 7 in fsr inc $1f ;increment file register ;1fh in bank 7
? 1999 scenix semiconductor, inc. all rights reserved. - 29 - www.scenix.com sx18ac / sx20ac / sx28ac must be initialized with appropriate values to point to the desired page before the jump occurs. this can be done easily w ith setb and clrb instructions or by writing a value to the status register. the device also has t he page instruction , which a utomatically selects the page in a single -c ycle execution. note: ?n? m ust be 0, 1, 2, or 3. 15.10.3 call operation the following happens when a call instruction is exe- cuted: ? the current value of the program counter is increment- ed and pushed onto the top of the stack . ? the lower eight bits of the label address are copied into the lower eight bits of the program counter . ? the ninth bit of the program counter i s cleared to zero . ? the page select bits (in status register) are copied into the upper two bits of the program counter. this means that the call destination must start in the lower half of any page. for example, 00h-0 ff h, 200h- 2 ff h, 400h-4ffh, etc. 15.10.4 page call operation when a subroutine that resides on a different page i s called, the page select bits must contain the proper val- ues to point to the desired page before the call instruction is executed. this can be done easily u sing setb and clrb instructions or writing a value to the status reg- ister. the device also has t he page instruction , which a utomatically selects the page in a single -c ycle execu- tion. note: ?n? must be 0, 1, 2, or 3. 15.11return instructions the device has several instructions for returning from subroutines and interrupt service routines. the return from subroutine instructions are ret (return without affecting w), retp (same as ret but affects pa1:pa0), reti (return from interrupt), retiw (return and add w to rtcc ), and retw #literal (return and place literal in w). the literal serves as an immediate data value from mem- ory. this instruction can be used for table lookup opera- tions. to do table lookup, the table must contain a string of retw #literal instructions. the first instruction just in front of the table c alculates the offset into the table. the table can be used as a result of a call. 15.12subroutine operation 15.12.1 push operation when a subroutine is called, the return address is pushed onto the subroutine stack. specifically, each address in the stack is moved to the next lower level in order to make room for the new address to be stored. stack 1 receives the contents of the program counter. stack 8 is overwritten with what was in stack 7. the con- tents of stack 8 are lost. 15.12.2 pop operation when a return instruction is executed the subroutine stack is popped. specifically, the contents of stack 1 are copied into the program counter and the contents of each stack level are moved to the next higher level. for exam- ple, stack 1 receives the contents of stack 2, etc., until stack 7 is overwritten with the contents of stack 8. stack 8 is left unchanged, so th e contents of stack 8 are d upli- cated in stack 7. status<6:5> jmp label pc<10:9> pc<8:0> page n status<6:5> jmp label pc<10:9> pc<8:0> status<6:5> 0 call label pc<10:9> pc<8> pc<7:0> page n status<6:5> 0 call label pc<10:9> pc<8> pc<7:0> pc<10:0> stack 1 stack 2 stack 3 stack 4 stack 5 stack 6 stack 7 stack 8
? 1999 scenix semiconductor, inc. all rights reserved. - 30 - www.scenix.com sx18ac / sx20ac / sx28ac 15.13comparison and conditional branch instructions the instruction set includes instructions such as decsz fr (decrement file register and skip if zero), incsz fr (increment file register and skip if zero), snb bit (bit test file register and skip if bit clear), and sb bit (bit test file register and skip if bit set). these instructions will cause the next instruction to be skipped if the test ed condition is true. if a skip instruction is immediately followed by a page or bank instruction (and the tested condition is true) then two instructions are skipped and the operation consumes three cycles. this is useful for conditional branching to another page where a page instruction precedes a jmp. if several page and bank instructions immediately follow a skip instruction then they are all skipped plus the next instruction and a cycle is consumed for each. 15.14logical instruction the instruction set contain a full complement of the logi- cal instructions (and, or, exclusive or), with the w register and a selected memory location (using either direct or indirect addressing) serving as the two oper- ands. 15.15shift and rotate instructions the instruction set includes instructions for left or right rotate-through-carry. 15.16complement and swap the device can perform o ne?s complement operation on the file register (fr) and w register. the mov w,<>fr instruction performs nibble-swap on the fr and puts the value into the w register. 15.17key to abbreviations and symbols pc<10:0> stack 1 stack 2 stack 3 stack 4 stack 5 stack 6 stack 7 stack 8 symbol description w working register fr file register (memory-mapped register in the range of 00h to ffh) pc lower eight bits of program counter (file regis- ter 02h) status status register (file register 03h) fsr file select register (file register 04h) c carry bit in status register (bit 0) dc digit carry bit in status register (bit 1) z zero bit in status register (bit 2 pd power down bit in status register (bit 3) to watchdog timeout bit in status register (bit 4) pa2:pa0 page select bits in status register (bits 7:5) option option register (not memory-mapped) wdt watchdog timer register (not memory- mapped) mode mode register (not memory-mapped) rx port control register pointer (ra, rb, or rc) ! non-memory-mapped register designator f file register address bit in opcode k constant value bit in opcode n numerical value bit in opcode b bit position selector bit in opcode . file register / bit selector separator in assem- bly language instruction # immediate literal designator in assembly lan- guage instruction lit literal value in assembly language instruction addr8 8-bit address in assembly language instruction addr9 9-bit address in assembly language instruction addr12 12-bit address in assembly language instruc- tion / logical 1?s complement | logical or ^ logical exclusive or & logical and <> swap high and low nibbles (4-bit segments) << rotate left through carry bit >> rotate right through carry bit - - decrement file register ++ increment file register
? 1999 scenix semiconductor, inc. all rights reserved. - 31 - www.scenix.com sx18ac / sx20ac / sx28ac 16.0instruction set summary table table16-1 lists all of the instructions, organized by cate- gory. for each instruction, the table shows the instruction mnemonic (as written in assembly language), a brief description of what the instruction does, the number of instruction cycles required for execution, the binary opcode, and the status bit s affected by the instruction. the ?cycles? column typically shows a value of 1, which means that the overall throughput for the instruction is one per clock cycle. in some cases, the exact number of cycles depends on the outcome of the instruction (such as the test-and-skip instructions) or the clocking mode (compatible or turbo). in those cases, all possible num- bers of cycles are shown in the table. the instruction execution time is derived by dividing the oscillator frequency by either one (turbo mode) or four (compatible mode). the divide-by factor is selected through the fuse word register. table16-1. the sx instruction set mnemonic, operands description cycles (compatible) cycles (turbo) opcode bits affected logical operations and fr, w and of fr and w into fr (fr = fr & w) 1 1 0001 011f ffff z and w, fr and of w and fr into w (w = w & fr) 1 1 0001 010f ffff z and w,#lit and of w and literal into w (w = w & lit) 1 1 1110 kkkk kkkk z not fr complement of fr into fr (fr = fr ^ ffh) 1 1 0010 011f ffff z or fr,w or of fr and w into fr (fr = fr | w) 1 1 0001 001f ffff z or w,fr or of w and fr into fr (w = w | fr) 1 1 0001 000f ffff z or w,#lit or of w and literal into w (w = w | lit) 1 1 1101 kkkk kkkk z xor fr,w xor of fr and w into fr (fr = fr ^ w) 1 1 0001 101f ffff z xor w,fr xor of w and fr into w (w = w ^ fr) 1 1 0001 100f ffff z xor w,#lit xor of w and literal into w (w = w ^ lit) 1 1 1111 kkkk kkkk z arithmetic and shift operations add fr,w add w to fr (fr = fr + w); carry bit is added if cf bit in fusex register is cleared to 0 1 1 0001 111f ffff c, dc, z add w,fr add fr to w (w = w + fr); carry bit is added if cf bit in fusex register is cleared to 0 1 1 0001 110f ffff c, dc, z clr fr clear fr (fr = 0) 1 1 0000 011f ffff z clr w clear w (w = 0) 1 1 0000 0100 0000 z clr !wdt clear watchdog timer, clear prescaler if as- signed to the watchdog (to = 1, pd = 1) 1 1 0000 0000 0100 to, pd dec fr decrement fr (fr = fr - 1) 1 1 0000 111f ffff z decsz fr decrement fr and skip if zero (fr = fr - 1 and skip next instruction if result is zero) 1 or 2 (skip) 1 or 2 (skip) 0010 111f ffff none inc fr increment fr (fr = fr + 1) 1 1 0010 101f ffff z incsz fr increment fr and skip if zero (fr = fr + 1 and skip next instruction if result is zero) 1 or 2 (skip) 1 or 2 (skip) 0011 111f ffff none rl fr rotate fr left through carry (fr = << fr) 1 1 0011 011f ffff c rr fr rotate fr right through carry (fr = >> fr) 1 1 0011 001f ffff c sub fr,w subtract w from fr (fr = fr - w); complement of the carry bit is subtracted if cf bit in fusex register is cleared to 0 1 1 0000 101f ffff c, dc, z swap fr swap high/low nibbles of fr (fr = <> fr) 1 1 0011 101f ffff none
? 1999 scenix semiconductor, inc. all rights reserved. - 32 - www.scenix.com sx18ac / sx20ac / sx28ac bitwise operations clrb fr.bit clear bit in fr (fr.bit = 0) 1 1 0100 bbbf ffff none sb fr.bit test bit in fr and skip if set (test fr.bit and skip next instruction if bit is 1) 1 or 2 (skip) 1 or 2 (skip) 0111 bbbf ffff none setb fr.bit set bit in fr (fr.bit = 1) 1 1 0101 bbbf ffff none snb fr.bit test bit in fr and skip if clear (test fr.bit and skip next instruction if bit is 0) 1 or 2 (skip) 1 or 2 (skip) 0110 bbbf ffff none data movement instructions mov fr,w move w to fr (fr = w) 1 1 0000 001f ffff none mov w,fr move fr to w (w = fr) 1 1 0010 000f ffff z mov w,fr-w move (fr-w) to w (w = fr - w); complement of carry bit is subtracted if cf bit in fusex register is cleared to 0 1 1 0000 100f ffff c, dc, z mov w,#lit move literal to w (w = lit) 1 1 1100 kkkk kkkk none mov w,/fr move complement of fr to w (w = fr ^ ffh) 1 1 0010 010f ffff z mov w,--fr move (fr-1) to w (w = fr - 1) 1 1 0000 110f ffff z mov w,++fr move (fr+1) to w (w = fr + 1) 1 1 0010 100f ffff z mov w,<>fr rotate fr right through carry and move to w (w = >> fr) 1 1 0011 000f ffff c mov w,<>fr swap high/low nibbles of fr and move to w (w = <> fr) 1 1 0011 100f ffff none mov w,m move mode register to w (w = mode), high nibble is cleared 1 1 0000 0100 0010 none movsz w,--fr move (fr-1) to w and skip if zero (w = fr -1 and skip next instruction if result is zero) 1 or 2 (skip) 1 2 (skip) 0010 110f ffff none movsz w,++fr move (fr+1) to w and skip if zero (w = fr + 1 and skip next instruction if result is zero) 1 or 2 (skip) 1 2 (skip) 0011 110f ffff none mov m,w move w to mode register (mode = w) 1 1 0000 0100 0011 none mov m,#lit move literal to mode register (mode = lit) 1 1 0000 0101 kkkk none mov !rx,w move w to port rx control register:rx <=> w (exchange w and wkpnd_b or cmp_b) or rx = w (move w to rx for all other port control reg- isters) 1 1 0000 0000 0fff none mov !option, w move w to option register (option = w) 1 1 0000 0000 0010 none test fr test fr for zero (fr = fr to set or clear z bit) 1 1 0010 001f ffff z program control instruction table16-1. the sx instruction set (continued) mnemonic, operands description cycles (compatible) cycles (turbo) opcode bits affected
? 1999 scenix semiconductor, inc. all rights reserved. - 33 - www.scenix.com sx18ac / sx20ac / sx28ac call addr8 call subroutine: top-of-stack = program counter + 1 pc(7:0) = addr8 program counter (8) = 0 program counter (10:9) = pa1:pa0 2 3 1001 kkkk kkkk none jmp addr9 jump to address: pc(7:0) = addr9(7:0) program counter (8) = addr9(8) program counter (10:9) = pa1:pa0 2 3 101k kkkk kkkk none nop no operation 1 1 0000 0000 0000 none ret return from subroutine (program counter = top-of-stack) 2 3 0000 0000 1100 none retp return from subroutine across page boundary (pa1:pa0 = top-of-stack (10:9) and program counter = top-of-stack) 2 3 0000 0000 1101 pa1, pa0 reti return from interrupt (restore w, status, fsr, and program counter from shadow regis- ters) 2 3 0000 0000 1110 all sta- tus, ex- cept to, pd retiw return from interrupt and add w to rtcc (re- store w, status, fsr, and program counter from shadow registers; and add w to rtcc) 2 3 0000 0000 1111 all sta- tus, ex- cept to, pd retw lit return from subroutine with literal in w (w = lit and program counter = top-of-stack) 2 3 1000 kkkk kkkk none system control instructions bank addr8 load bank number into fsr(7:5) fsr(7:5) = addr8(7:5) 1 1 0000 0001 1nnn none iread read word from instruction memory mode:w = data at (mode:w) 1 4 0000 0100 0001 none page addr12 load page number into status(7:5) status(7:5) = addr12(11:9) 1 1 0000 0001 0nnn pa1, pa0 sleep power down mode wdt = 00h, to = 1, stop oscillator (pd = 0, clears prescaler if assigned) 1 1 0000 0000 0011 to, pd table16-1. the sx instruction set (continued) mnemonic, operands description cycles (compatible) cycles (turbo) opcode bits affected
? 1999 scenix semiconductor, inc. all rights reserved. - 34 - www.scenix.com sx18ac / sx20ac / sx28ac 16.1equivalent assembler mnemonics some assemblers support additional instruction mne- monics that are special cases of existing instructions or alternative mnemonics for standard ones. for example, an assembler might support the mnemonic ?clc? (clear carry), which is interpreted the same as the instruction ?clrb $03.0? (clear bit 0 in the status register). some of the commonly supported equivalent assembler mnemon- ics are described in table 16-2. table16-2. equivalent assembler mnemonics syntax description equivalent cycles clc clear carry bit clrb $03.0 1 clz clear zero bit clrb $03.2 1 jmp w jump indirect w mov $02,w 4 or 3 (note 1) jmp pc+w jump indirect w relative add $02,w 4 or 3 (note 1) mode imm4 move immediate to mode register mov m,#lit 1 not w complement w xor w,#$ff 1 sc skip if carry bit set sb $03.0 1 or 2 (note 2) skip skip next instruction snb $02.0 or sb $02.0 4 or 2 (note 3) note1: the jmp w or jmp pc+w instruction takes 4 cycles in the ?compatible? clocking mode or 3 cycles in the ?turbo? clocking mode. note2: the sc instruction takes 1 cycle if the tested condition is false or 2 cycles if the tested condition is true. note3: the assembler converts the skip instruction into a snb or sb instruction that tests the least significant bit of the program counter, choosing snb or sb so that the tested condition is always true. the instruction takes 4 cycles in the ?compatible? clocking mode or 2 cycles in the ?turbo? clocking mode.
? 1999 scenix semiconductor, inc. all rights reserved. - 35 - www.scenix.com sx18ac / sx20ac / sx28ac 17.0electrical characteristics 17.1absolute maximum ratings ambient temperature under bias -40 c to +85 c storage temperature -65 c to +150 c voltage on v dd with respect to v ss 0 v to +7.5v voltage on osc1 with respect to v ss 0 v to +12.5v voltage on mclr with respect to v ss 0 v to +14v voltage on all other pins with respect to v ss 0.6 v to ( v dd + 0.6v)v total power dissipation tbd mw max. current out of v ss pin 100ma max. current into v dd pin 100ma max. dc current into an input pin (with internal protection diode forward biased) + 500 m a max. allowable sink current per i/o pin 45ma max. allowable source current per i/o pin 45 ma
? 1999 scenix semiconductor, inc. all rights reserved. - 36 - www.scenix.com sx18ac / sx20ac / sx28ac 17.2dc characteristics operating temperature 0 c <= ta <= +70 c (commercial) symbol parameter conditions min typ max units v dd supply voltage 2.5 - 5.5 v v por v dd start voltage to ensure power-on reset v ss - - v s vdd v dd rise rate 0.05 - - v/ms i dd supply current, active v dd = 5.0v, f osc = 50 mhz v dd = 5.0v, f osc = 4 mhz internal v dd = 2.5v, f osc = 20 mhz - 65 6 12 - ma ma ma i pd supply current, power down v dd = 5.5v, wdt enabled v dd = 5.5v, wdt disabled v dd = 2.5v, wdt enabled v dd = 2.5v, wdt disabled - tbd 1.0 tbd 500 - a a a na v ih, v il input levels mclr, osc1, rtcc logic high logic low all other inputs cmos logic high logic low ttl logic high logic low 0.8v dd v ss 0.7v dd v ss 2.0 v ss v dd 0.2v dd v dd 0.3v dd v dd 0.8 v v v v v v i il input leakage current v in = v dd or v ss -1.0 +1.0 a i ip weak pullup current v dd = 5.0v, v in = 0v v dd = 2.5v, v in = 0v 400 80 a a v oh output high voltage osc2, ports b, c port a ioh = 20ma, vdd = 4.5v ioh = 12ma, vdd = 2.5v ioh = 30ma, vdd = 4.5 ioh = 18 ma, vdd = 2.5v vdd-0.7 vdd-0.7 vdd-0.7 vdd-0.7 v v v v v ol output low voltage all ports, osc2 i ol = 30ma, vdd = 4.5v iol = 18ma, vdd = 2.5v 0.6 0.6 v v
? 1999 scenix semiconductor, inc. all rights reserved. - 37 - www.scenix.com sx18ac / sx20ac / sx28ac 17.3 ac characteristics operating temperature 0 c <= ta <= +70 c (commercial) note: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. symbol parameter min typ max units conditions f osc external clkin frequency dc - 4.0 10 24 50 32 1.0 mhz mhz mhz mhz khz mhz rc xt1 xt2 hs lp1 lp2 oscillator frequency dc 0.032 1.0 1.0 dc 0.032 - 4.0 10.0 24.0 50 32 1.0 mhz mhz mhz mhz khz mhz rc xt1 xt2 hs lp1 lp2 t osc external clkin period 250 100 41.7 20 31.25 1.0 - - ns ns ns ns s s rc xt1 xt2 hs lp1 lp2 oscillator period 250 100 41.7 20 31.25 1.0 - - 31.25 1.0 1.0 - 31.25 ns s s s s s rc xt1 xt2 hs lp1 lp2 t osl , t osh clock in (osc1) low or high time 50 8.0 2.0 - - ns ns s xt1/xt2 hs lp1/lp2 t osr , t osf clock in (osc1) rise or fall time - - 25 25 50 ns ns s xt1/xt2 hs lp1/lp2
? 1999 scenix semiconductor, inc. all rights reserved. - 38 - www.scenix.com sx18ac / sx20ac / sx28ac 17.4comparator dc and ac specifications parameter conditions min typ max units input offset voltage 0.4v < vin < vdd ? 1.5v +/- 10 +/- 25 mv input common mode voltage range 0.4 vcc ? 1.3 v voltage gain 300k v/v dc supply current (enabled) vdd = 5.5v 120 a response time v overdrive = 25mv 250 ns
? 1999 scenix semiconductor, inc. all rights reserved. - 39 - www.scenix.com sx18ac / sx20ac / sx28ac 18.0package dimensions ( dimensions are in inches/(millimeters) 28 10 9 1 sx18ac/so 0.090 - 0.094 (2.29 - 2.39) 0.292 - 0.299 (7.42 - 7.59) 0.451 - 0.461 (11.46 - 11.71) 0.090 - 0.094 (2.29 - 2.39) 0.014 - 0.019 (0.35 - 0.48) 0.0050 - 0.0115 (0.127 - 0.292) 0.400 - 0.410 (10.16 - 10.41) 0.292 - 0.299 7.42 - 7.59) 0.045 - 0.055 (1.143 - 1.397) 0.035 - 0.045 (0.890 - 1.143) 0.050 bsc (1.27 bsc) sx18ac/dp 18 1 10 9 0.008 - 0.012 (0.20 - 0.31) 0.895 - 0.905 (22.73 - 22.99) 0.430 max . (10.92 max .) 0.300 bsc at 90 o (7.62 bsc at 90 o ) [ ] 0.240 - 0.260 (6.10 -6.60) 0.130 nom. (3.3 nom.) 0.125 - 0.135 (3.17 - 3.43) 0.015 min. (0.38 min.) 0.100 bsc (2.54 bsc) 0.055 -0.065 (1.39 - 1.65) 0.015 - 0.022 (0.38 - 0.56) 0.170 max . (4.32 max .)
? 1999 scenix semiconductor, inc. all rights reserved. - 40 - www.scenix.com sx18ac / sx20ac / sx28ac 20 1 10 11 sx20ac/ss 0.205 - 0.212 (5.20 - 5.38) 0.066 - 0.070 (1.68 - 1.78) 12 o - 16 o 0.066 - 0.070 (1.68 - 1.78) 0.0256 bsc (0.65 bsc) 0.010 - 0.015 (0.25 - 0.38) 0.002 - 0.008 (0.05 - 0.21) 0.278 - 0.289 (7.07 - 7.33) 0.301 - 0.311 (7.65 - 7.90) 0.205 - 0.212 (5.20 - 5.38) 0.039 (1.00) 0.039 (1.00) 28 15 14 1 sx28ac/so 0.090 - 0.094 (2.29 - 2.39) 0.292 - 0.299 (7.42 - 7.59) 0.701 - 0.710 (17.81 - 18.06) 0.090 - 0.094 (2.29 - 2.39) 0.014 - 0.019 (0.35 - 0.48) 0.0050 - 0.0115 (0.127 - 0.292) 0.40 - 0.41 (10.16 - 10.41) 0.292 - 0.299 7.42 - 7.59) 0.045 - 0.055 (1.143 - 1.397) 0.035 - 0.045 (0.890 - 1.143) 0.050 bsc (1.27 bsc)
? 1999 scenix semiconductor, inc. all rights reserved. - 41 - www.scenix.com sx18ac / sx20ac / sx28ac 28 15 1 14 sx28ac/dp 0.430 max . (10.92 max .) 0.009 - 0.014 (0.23 - 0.36) 1.360 - 1.370 (34.54 - 34.80) 0.280 - 0.295 (7.11 - 7.49) 0.130 nom. (3.3 nom.) 0.120 - 0.135 (3.05 - 3.43) 0.015 - 0.021 (0.38 - 0.53) 0.045 - 0.055 (1.14 - 1.40) 0.100 bsc (2.54 bsc) 0.180 max . (4.57 max .) 0.020 min. (0.51 min.) 0.300 bsc at 90 o (7.62 bsc at 90 o ) [ ] 28 15 14 1 sx28ac/ss 0.205 - 0.212 (5.20 - 5.38) 0.066 - 0.070 (1.68 - 1.78) 0.066 - 0.070 (1.68 - 1.78) 0.0256 bsc (0.65 bsc) 0.010 - 0.015 (0.25 - 0.38) 0.002 - 0.008 (0.05 - 0.21) 0.397 - 0.407 (10.07 - 10.33) 0.301 - 0.311 (7.65 - 7.90) 0.205 - 0.212 (5.20 - 5.38) 0.039 (1.00) 0.039 (1.00) 12 o - 16 o
? 1999 scenix semiconductor, inc. all rights reserved. - 42 - www.scenix.com sales and tech support contact information for the latest contact and support information on sx devices, please visit the scenix semiconductor website at www.scenix.com . the site contains technical literature, local sales contacts, tech support and many other features. scenix semiconductor, inc. 3160 de la cruz blvd., suite #200, santa clara, ca 95054 contact: sales@scenix.com http://www.scenix.com tel.: (408) 327-8888 fax: (408) 327-8880 sx18ac / sx20ac / sx28ac lit #: sxl-ds01-03 sales and tech support contact information for the latest contact and support information on sx devices, please visit the scenix semiconductor website at www.scenix.com . the site contains technical literature, local sales contacts, tech support and many other features. scenix semiconductor, inc. 3160 de la cruz blvd., suite #200, santa clara, ca 95054 contact: sales@scenix.com http://www.scenix.com tel.: (408) 327-8888 fax: (408) 327-8880

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